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	GPU: Macros are specific to the Maxwell3D engine, so handle them internally.
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				@ -64,35 +64,6 @@ void GPU::WriteReg(u32 method, u32 subchannel, u32 value) {
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    }
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}
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void GPU::CallMethod(u32 method, u32 subchannel, const std::vector<u32>& parameters) {
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    LOG_WARNING(HW_GPU, "Processing method %08X on subchannel %u num params %zu", method,
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                subchannel, parameters.size());
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    if (method < static_cast<u32>(BufferMethods::CountBufferMethods)) {
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        // TODO(Subv): Research and implement these methods.
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        LOG_ERROR(HW_GPU, "Special buffer methods other than Bind are not implemented");
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        return;
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    }
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    ASSERT(bound_engines.find(subchannel) != bound_engines.end());
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    const EngineID engine = bound_engines[subchannel];
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    switch (engine) {
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    case EngineID::FERMI_TWOD_A:
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        fermi_2d->CallMethod(method, parameters);
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        break;
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    case EngineID::MAXWELL_B:
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        maxwell_3d->CallMethod(method, parameters);
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        break;
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    case EngineID::MAXWELL_COMPUTE_B:
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        maxwell_compute->CallMethod(method, parameters);
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        break;
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    default:
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        UNIMPLEMENTED();
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    }
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}
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void GPU::ProcessCommandList(GPUVAddr address, u32 size) {
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    // TODO(Subv): PhysicalToVirtualAddress is a misnomer, it converts a GPU VAddr into an
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    // application VAddr.
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@ -8,7 +8,6 @@ namespace Tegra {
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namespace Engines {
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void Fermi2D::WriteReg(u32 method, u32 value) {}
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void Fermi2D::CallMethod(u32 method, const std::vector<u32>& parameters) {}
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} // namespace Engines
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} // namespace Tegra
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@ -4,7 +4,6 @@
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#pragma once
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#include <vector>
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#include "common/common_types.h"
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namespace Tegra {
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@ -17,13 +16,6 @@ public:
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    /// Write the value to the register identified by method.
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    void WriteReg(u32 method, u32 value);
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    /**
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     * Handles a method call to this engine.
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     * @param method Method to call
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     * @param parameters Arguments to the method call
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     */
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    void CallMethod(u32 method, const std::vector<u32>& parameters);
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};
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} // namespace Engines
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@ -8,28 +8,59 @@
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namespace Tegra {
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namespace Engines {
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/// First register id that is actually a Macro call.
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constexpr u32 MacroRegistersStart = 0xE00;
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const std::unordered_map<u32, Maxwell3D::MethodInfo> Maxwell3D::method_handlers = {
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    {0xE24, {"SetShader", 5, &Maxwell3D::SetShader}},
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};
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Maxwell3D::Maxwell3D(MemoryManager& memory_manager) : memory_manager(memory_manager) {}
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void Maxwell3D::CallMethod(u32 method, const std::vector<u32>& parameters) {
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void Maxwell3D::AttemptMethodCall(u32 method, const std::vector<u32>& parameters) {
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    // TODO(Subv): Write an interpreter for the macros uploaded via registers 0x45 and 0x47
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    auto itr = method_handlers.find(method);
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    if (itr == method_handlers.end()) {
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        LOG_ERROR(HW_GPU, "Unhandled method call %08X", method);
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        return;
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    }
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    ASSERT_MSG(itr != method_handlers.end(), "Unhandled method call %08X", method);
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    // Only execute the macro handler once we've been fed the expected number of parameters.
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    if (itr->second.arguments != parameters.size())
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        return;
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    ASSERT(itr->second.arguments == parameters.size());
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    (this->*itr->second.handler)(parameters);
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    // Reset the current macro and its parameters.
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    executing_macro = 0;
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    macro_params.clear();
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}
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void Maxwell3D::WriteReg(u32 method, u32 value) {
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    ASSERT_MSG(method < Regs::NUM_REGS,
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               "Invalid Maxwell3D register, increase the size of the Regs structure");
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    // It is an error to write to a register other than the current macro's ARG register before it
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    // has finished execution.
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    if (executing_macro != 0) {
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        ASSERT(method == executing_macro + 1);
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    }
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    // Methods after 0xE00 are special, they're actually triggers for some microcode that was
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    // uploaded to the GPU during initialization.
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    if (method >= MacroRegistersStart) {
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        // We're trying to execute a macro
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        if (executing_macro == 0) {
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            // A macro call must begin by writing the macro method's register, not its argument.
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            ASSERT_MSG((method % 2) == 0,
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                       "Can't start macro execution by writing to the ARGS register");
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            executing_macro = method;
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        }
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        macro_params.push_back(value);
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        // Try to call the macro with the current number of parameters.
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        AttemptMethodCall(executing_macro, macro_params);
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        return;
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    }
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    regs.reg_array[method] = value;
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#define MAXWELL3D_REG_INDEX(field_name) (offsetof(Regs, field_name) / sizeof(u32))
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@ -23,13 +23,6 @@ public:
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    /// Write the value to the register identified by method.
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    void WriteReg(u32 method, u32 value);
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    /**
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     * Handles a method call to this engine.
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     * @param method Method to call
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     * @param parameters Arguments to the method call
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     */
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    void CallMethod(u32 method, const std::vector<u32>& parameters);
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    /// Register structure of the Maxwell3D engine.
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    /// TODO(Subv): This structure will need to be made bigger as more registers are discovered.
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    struct Regs {
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@ -166,7 +159,11 @@ public:
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                    INSERT_PADDING_WORDS(7);
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                } cb_bind[MaxShaderStage];
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                INSERT_PADDING_WORDS(0x50A);
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                INSERT_PADDING_WORDS(0x56);
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                u32 tex_cb_index;
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                INSERT_PADDING_WORDS(0x4B3);
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            };
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            std::array<u32, NUM_REGS> reg_array;
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        };
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@ -201,6 +198,19 @@ public:
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private:
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    MemoryManager& memory_manager;
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    /// Macro method that is currently being executed / being fed parameters.
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    u32 executing_macro = 0;
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    /// Parameters that have been submitted to the macro call so far.
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    std::vector<u32> macro_params;
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    /**
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     * Attempts a method call to this engine. Will return without doing anything if the number of
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     * parameters doesn't match what is expected for the method.
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     * @param method Method to call
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     * @param parameters Arguments to the method call
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     */
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    void AttemptMethodCall(u32 method, const std::vector<u32>& parameters);
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    /// Handles a write to the QUERY_GET register.
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    void ProcessQueryGet();
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@ -234,6 +244,7 @@ ASSERT_REG_POSITION(vertex_array_limit[0], 0x7C0);
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ASSERT_REG_POSITION(shader_config[0], 0x800);
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ASSERT_REG_POSITION(const_buffer, 0x8E0);
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ASSERT_REG_POSITION(cb_bind[0], 0x904);
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ASSERT_REG_POSITION(tex_cb_index, 0x982);
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#undef ASSERT_REG_POSITION
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@ -8,7 +8,6 @@ namespace Tegra {
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namespace Engines {
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void MaxwellCompute::WriteReg(u32 method, u32 value) {}
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void MaxwellCompute::CallMethod(u32 method, const std::vector<u32>& parameters) {}
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} // namespace Engines
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} // namespace Tegra
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@ -4,7 +4,6 @@
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#pragma once
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#include <vector>
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#include "common/common_types.h"
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namespace Tegra {
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@ -17,13 +16,6 @@ public:
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    /// Write the value to the register identified by method.
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    void WriteReg(u32 method, u32 value);
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    /**
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     * Handles a method call to this engine.
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     * @param method Method to call
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     * @param parameters Arguments to the method call
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     */
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    void CallMethod(u32 method, const std::vector<u32>& parameters);
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};
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} // namespace Engines
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@ -41,9 +41,6 @@ private:
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    /// Writes a single register in the engine bound to the specified subchannel
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    void WriteReg(u32 method, u32 subchannel, u32 value);
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    /// Calls a method in the engine bound to the specified subchannel with the input parameters.
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    void CallMethod(u32 method, u32 subchannel, const std::vector<u32>& parameters);
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    /// Mapping of command subchannels to their bound engine ids.
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    std::unordered_map<u32, EngineID> bound_engines;
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