mirror of
https://git.tardis.systems/mirrors/yuzu
synced 2025-10-31 10:44:49 +01:00
added ARM11 MMU from skyeye
This commit is contained in:
bunnei
parent
bd38abf249
commit
328c415c74
@ -144,6 +144,7 @@
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<ClCompile Include="src\arm\armsupp.cpp" />
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<ClCompile Include="src\arm\armvirt.cpp" />
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<ClCompile Include="src\arm\disassembler\arm_disasm.cpp" />
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<ClCompile Include="src\arm\mmu\arm1176jzf_s_mmu.cpp" />
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<ClCompile Include="src\core.cpp" />
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<ClCompile Include="src\core_timing.cpp" />
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<ClCompile Include="src\elf\elf_reader.cpp" />
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@ -37,6 +37,9 @@
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<ClCompile Include="src\arm\armos.cpp">
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<Filter>arm</Filter>
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</ClCompile>
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<ClCompile Include="src\arm\mmu\arm1176jzf_s_mmu.cpp">
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<Filter>arm\mmu</Filter>
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</ClCompile>
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</ItemGroup>
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<ItemGroup>
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<Filter Include="arm">
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@ -72,7 +72,7 @@ mmu_init (ARMul_State * state)
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/* case 0x560f5810: */
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case 0x0007b000:
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NOTICE_LOG(ARM11, "SKYEYE: use arm11jzf-s mmu ops\n");
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//state->mmu.ops = arm1176jzf_s_mmu_ops;
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state->mmu.ops = arm1176jzf_s_mmu_ops;
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_dbg_assert_msg_(ARM11, false, "ImplementMe: arm1176jzf_s_mmu_ops!");
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break;
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@ -104,15 +104,15 @@ typedef enum mmu_regnum_t
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/*virt_addr exchange according to CP15.R13(process id virtul mapping)*/
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#define PID_VA_MAP_MASK 0xfe000000
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#define mmu_pid_va_map(va) ({\
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ARMword ret; \
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if ((va) & PID_VA_MAP_MASK)\
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ret = (va); \
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else \
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ret = ((va) | (state->mmu.process_id & PID_VA_MAP_MASK));\
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ret;\
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})
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//#define mmu_pid_va_map(va) ({\
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// ARMword ret; \
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// if ((va) & PID_VA_MAP_MASK)\
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// ret = (va); \
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// else \
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// ret = ((va) | (state->mmu.process_id & PID_VA_MAP_MASK));\
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// ret;\
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//})
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#define mmu_pid_va_map(va) ((va) & PID_VA_MAP_MASK) ? (va) : ((va) | (state->mmu.process_id & PID_VA_MAP_MASK))
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/* FS[3:0] in the fault status register: */
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@ -21,10 +21,13 @@
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#include <assert.h>
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#include <string.h>
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#include <stdint.h>
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#include <skyeye_ram.h>
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#include "armdefs.h"
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#include "bank_defs.h"
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#include "mem_map.h"
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#include "arm/skyeye_defs.h"
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#include "arm/armdefs.h"
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//#include "bank_defs.h"
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#if 0
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#define TLB_SIZE 1024 * 1024
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#define ASID 255
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@ -59,44 +62,10 @@ static inline void insert_tlb(ARMul_State* state, ARMword va, ARMword pa){
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#endif
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#define BANK0_START 0x50000000
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static void* mem_ptr = NULL;
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//static void mem_read_raw(uint32_t offset, uint32_t &value, int size)
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static void mem_read_raw(int size, uint32_t offset, uint32_t *value)
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{
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#if 0
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if(mem_ptr == NULL)
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mem_ptr = (uint8_t*)get_dma_addr(BANK0_START);
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//printf("In %s, offset=0x%x, mem_ptr=0x%llx\n", __FUNCTION__, offset, mem_ptr);
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if(offset >= 0x50000000 && offset < 0x70000000){
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mem_read(size, offset, value);
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}
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else{
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bus_read(size, offset, value);
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}
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#endif
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bus_read(size, offset, value);
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}
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//static void mem_write_raw(uint32_t offset, uint32_t value, int size)
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static void mem_write_raw(int size, uint32_t offset, uint32_t value)
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{
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#if 0
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if(mem_ptr == NULL)
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mem_ptr = (uint8_t*)get_dma_addr(BANK0_START);
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//printf("In %s, offset=0x%x, mem_ptr=0x%llx\n", __FUNCTION__, offset, mem_ptr);
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if(offset >= 0x50000000 && offset < 0x70000000){
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mem_write(size, offset, value);
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}
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else{
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bus_write(size, offset, value);
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}
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#endif
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bus_write(size, offset, value);
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}
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static int exclusive_detect(ARMul_State* state, ARMword addr){
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int i;
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#if 0
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for(i = 0; i < 128; i++){
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for(int i = 0; i < 128; i++){
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if(state->exclusive_tag_array[i] == addr)
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return 0;
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}
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@ -108,9 +77,8 @@ static int exclusive_detect(ARMul_State* state, ARMword addr){
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}
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static void add_exclusive_addr(ARMul_State* state, ARMword addr){
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int i;
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#if 0
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for(i = 0; i < 128; i++){
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for(int i = 0; i < 128; i++){
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if(state->exclusive_tag_array[i] == 0xffffffff){
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state->exclusive_tag_array[i] = addr;
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//printf("In %s, add addr 0x%x\n", __func__, addr);
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@ -262,10 +230,11 @@ mmu_translate (ARMul_State *state, ARMword virt_addr, ARMword *phys_addr, int *a
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}
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/* l1desc = mem_read_word (state, l1addr); */
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if(state->space.conf_obj != NULL)
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if (state->space.conf_obj != NULL)
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state->space.read(state->space.conf_obj, l1addr, &l1desc, 4);
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else
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mem_read_raw(32, l1addr, &l1desc);
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l1desc = Memory::Read32(l1addr); //mem_read_raw(32, l1addr, &l1desc);
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#if 0
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if (virt_addr == 0xc000d2bc) {
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printf("mmu_control is %x\n", state->mmu.translation_table_ctrl);
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@ -298,7 +267,8 @@ mmu_translate (ARMul_State *state, ARMword virt_addr, ARMword *phys_addr, int *a
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if(state->space.conf_obj != NULL)
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state->space.read(state->space.conf_obj, l2addr, &l2desc, 4);
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else
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mem_read_raw(32, l2addr, &l2desc);
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l2desc = Memory::Read32(l2addr); //mem_read_raw(32, l2addr, &l2desc);
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/* chy 2003-09-02 for xscale */
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*ap = (l2desc >> 4) & 0x3;
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*sop = 1; /* page */
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@ -385,7 +355,7 @@ arm1176jzf_s_mmu_load_instr (ARMul_State *state, ARMword va, ARMword *instr)
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static int debug_count = 0; /* used for debug */
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d_msg ("va = %x\n", va);
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DEBUG_LOG(ARM11, "va = %x\n", va);
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va = mmu_pid_va_map (va);
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if (MMU_Enabled) {
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@ -393,7 +363,7 @@ arm1176jzf_s_mmu_load_instr (ARMul_State *state, ARMword va, ARMword *instr)
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// sleep(1);
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/* align check */
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if ((va & (WORD_SIZE - 1)) && MMU_Aligned) {
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d_msg ("align\n");
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DEBUG_LOG(ARM11, "align\n");
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return ALIGNMENT_FAULT;
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} else
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va &= ~(WORD_SIZE - 1);
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@ -401,7 +371,7 @@ arm1176jzf_s_mmu_load_instr (ARMul_State *state, ARMword va, ARMword *instr)
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/* translate tlb */
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fault = mmu_translate (state, va, &pa, &ap, &sop);
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if (fault) {
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d_msg ("translate\n");
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DEBUG_LOG(ARM11, "translate\n");
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printf("va=0x%x, icounter=%lld, fault=%d\n", va, state->NumInstrs, fault);
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return fault;
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}
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@ -420,7 +390,7 @@ arm1176jzf_s_mmu_load_instr (ARMul_State *state, ARMword va, ARMword *instr)
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/*check access */
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fault = check_access (state, va, tlb, 1);
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if (fault) {
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d_msg ("check_fault\n");
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DEBUG_LOG(ARM11, "check_fault\n");
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return fault;
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}
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#endif
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@ -435,9 +405,9 @@ arm1176jzf_s_mmu_load_instr (ARMul_State *state, ARMword va, ARMword *instr)
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if(state->space.conf_obj == NULL)
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state->space.read(state->space.conf_obj, pa, instr, 4);
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else
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mem_read_raw(32, pa, instr);
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*instr = Memory::Read32(pa); //mem_read_raw(32, pa, instr);
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return 0;
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return NO_FAULT;
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}
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static fault_t
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@ -474,7 +444,7 @@ arm1176jzf_s_mmu_read (ARMul_State *state, ARMword va, ARMword *data,
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ARMword perm; /* physical addr access permissions */
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int ap, sop;
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d_msg ("va = %x\n", va);
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DEBUG_LOG(ARM11, "va = %x\n", va);
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va = mmu_pid_va_map (va);
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real_va = va;
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@ -489,25 +459,24 @@ arm1176jzf_s_mmu_read (ARMul_State *state, ARMword va, ARMword *data,
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if(state->space.conf_obj != NULL)
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state->space.read(state->space.conf_obj, va, data, 1);
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else
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mem_read_raw(8, va, data);
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*data = Memory::Read8(va); //mem_read_raw(8, va, data);
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else if (datatype == ARM_HALFWORD_TYPE)
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/* *data = mem_read_halfword (state, va); */
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if(state->space.conf_obj != NULL)
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state->space.read(state->space.conf_obj, va, data, 2);
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else
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mem_read_raw(16, va, data);
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*data = Memory::Read16(va); //mem_read_raw(16, va, data);
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else if (datatype == ARM_WORD_TYPE)
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/* *data = mem_read_word (state, va); */
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if(state->space.conf_obj != NULL)
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state->space.read(state->space.conf_obj, va, data, 4);
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else
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mem_read_raw(32, va, data);
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*data = Memory::Read32(va); //mem_read_raw(32, va, data);
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else {
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printf ("SKYEYE:1 arm1176jzf_s_mmu_read error: unknown data type %d\n", datatype);
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skyeye_exit (-1);
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ERROR_LOG(ARM11, "SKYEYE:1 arm1176jzf_s_mmu_read error: unknown data type %d\n", datatype);
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}
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return 0;
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return NO_FAULT;
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}
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// printf("MMU enabled.\n");
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// sleep(1);
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@ -515,7 +484,7 @@ arm1176jzf_s_mmu_read (ARMul_State *state, ARMword va, ARMword *data,
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/* align check */
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if (((va & 3) && (datatype == ARM_WORD_TYPE) && MMU_Aligned) ||
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((va & 1) && (datatype == ARM_HALFWORD_TYPE) && MMU_Aligned)) {
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d_msg ("align\n");
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DEBUG_LOG(ARM11, "align\n");
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return ALIGNMENT_FAULT;
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}
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@ -544,7 +513,7 @@ arm1176jzf_s_mmu_read (ARMul_State *state, ARMword va, ARMword *data,
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}
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#endif
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if (fault) {
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d_msg ("translate\n");
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DEBUG_LOG(ARM11, "translate\n");
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//printf("mmu read fault at %x\n", va);
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//printf("fault is %d\n", fault);
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return fault;
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@ -574,24 +543,23 @@ skip_translation:
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if(state->space.conf_obj != NULL)
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state->space.read(state->space.conf_obj, pa | (real_va & 3), data, 1);
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else
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mem_read_raw(8, pa | (real_va & 3), data);
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*data = Memory::Read8(pa | (real_va & 3)); //mem_read_raw(8, pa | (real_va & 3), data);
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/* mem_read_raw(32, pa | (real_va & 3), data); */
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} else if (datatype == ARM_HALFWORD_TYPE) {
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/* *data = mem_read_halfword (state, pa | (real_va & 2)); */
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if(state->space.conf_obj != NULL)
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state->space.read(state->space.conf_obj, pa | (real_va & 3), data, 2);
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else
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mem_read_raw(16, pa | (real_va & 3), data);
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*data = Memory::Read16(pa | (real_va & 3)); //mem_read_raw(16, pa | (real_va & 3), data);
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/* mem_read_raw(32, pa | (real_va & 2), data); */
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} else if (datatype == ARM_WORD_TYPE)
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/* *data = mem_read_word (state, pa); */
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if(state->space.conf_obj != NULL)
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state->space.read(state->space.conf_obj, pa , data, 4);
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else
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mem_read_raw(32, pa, data);
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*data = Memory::Read32(pa); //mem_read_raw(32, pa, data);
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else {
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printf ("SKYEYE:2 arm1176jzf_s_mmu_read error: unknown data type %d\n", datatype);
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skyeye_exit (-1);
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ERROR_LOG(ARM11, "SKYEYE:2 arm1176jzf_s_mmu_read error: unknown data type %d\n", datatype);
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}
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if(0 && (va == 0x2869c)){
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printf("In %s, pa is %x va=0x%x, value is %x pc %x, instr=0x%x\n", __FUNCTION__, pa, va, *data, state->Reg[15], state->CurrInstr);
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@ -614,7 +582,7 @@ skip_translation:
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}
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#endif
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return 0;
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return NO_FAULT;
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}
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@ -661,7 +629,7 @@ arm1176jzf_s_mmu_write (ARMul_State *state, ARMword va, ARMword data,
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}
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#endif
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d_msg ("va = %x, val = %x\n", va, data);
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DEBUG_LOG(ARM11, "va = %x, val = %x\n", va, data);
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va = mmu_pid_va_map (va);
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real_va = va;
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@ -672,22 +640,21 @@ arm1176jzf_s_mmu_write (ARMul_State *state, ARMword va, ARMword data,
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if(state->space.conf_obj != NULL)
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state->space.write(state->space.conf_obj, va, &data, 1);
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else
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mem_write_raw(8, va, data);
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Memory::Write8(va, data);
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else if (datatype == ARM_HALFWORD_TYPE)
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/* mem_write_halfword (state, va, data); */
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if(state->space.conf_obj != NULL)
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state->space.write(state->space.conf_obj, va, &data, 2);
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else
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mem_write_raw(16, va, data);
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Memory::Write16(va, data);
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else if (datatype == ARM_WORD_TYPE)
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/* mem_write_word (state, va, data); */
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if(state->space.conf_obj != NULL)
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state->space.write(state->space.conf_obj, va, &data, 4);
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else
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mem_write_raw(32, va, data);
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Memory::Write32(va, data);
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else {
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printf ("SKYEYE:1 arm1176jzf_s_mmu_write error: unknown data type %d\n", datatype);
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skyeye_exit (-1);
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ERROR_LOG (ARM11, "SKYEYE:1 arm1176jzf_s_mmu_write error: unknown data type %d\n", datatype);
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}
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goto finished_write;
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//return 0;
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@ -696,7 +663,7 @@ arm1176jzf_s_mmu_write (ARMul_State *state, ARMword va, ARMword data,
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/* if ((va & (WORD_SIZE - 1)) && MMU_Aligned){ */
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if (((va & 3) && (datatype == ARM_WORD_TYPE) && MMU_Aligned) ||
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((va & 1) && (datatype == ARM_HALFWORD_TYPE) && MMU_Aligned)) {
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d_msg ("align\n");
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DEBUG_LOG(ARM11, "align\n");
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return ALIGNMENT_FAULT;
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}
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va &= ~(WORD_SIZE - 1);
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@ -721,7 +688,7 @@ arm1176jzf_s_mmu_write (ARMul_State *state, ARMword va, ARMword data,
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}
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#endif
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if (fault) {
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d_msg ("translate\n");
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DEBUG_LOG(ARM11, "translate\n");
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//printf("mmu write fault at %x\n", va);
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return fault;
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}
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@ -740,7 +707,7 @@ arm1176jzf_s_mmu_write (ARMul_State *state, ARMword va, ARMword data,
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/* tlb check access */
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fault = check_access (state, va, tlb, 0);
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if (fault) {
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d_msg ("check_access\n");
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DEBUG_LOG(ARM11, "check_access\n");
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return fault;
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}
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#endif
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@ -771,7 +738,7 @@ skip_translation:
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else{
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state->Reg[dest_reg] = 1;
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//printf("In %s, try to strex a monitored address 0x%x\n", __FUNCTION__, pa);
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return 0;
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return NO_FAULT;
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}
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}
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@ -783,7 +750,7 @@ skip_translation:
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if(state->space.conf_obj != NULL)
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state->space.write(state->space.conf_obj, (pa | (real_va & 3)), &data, 1);
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else
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mem_write_raw(8, (pa | (real_va & 3)), data);
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Memory::Write8((pa | (real_va & 3)), data);
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} else if (datatype == ARM_HALFWORD_TYPE)
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/* mem_write_halfword (state,
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@ -794,13 +761,13 @@ skip_translation:
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if(state->space.conf_obj != NULL)
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state->space.write(state->space.conf_obj, (pa | (real_va & 3)), &data, 2);
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else
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mem_write_raw(16, (pa | (real_va & 3)), data);
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Memory::Write16((pa | (real_va & 3)), data);
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else if (datatype == ARM_WORD_TYPE)
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/* mem_write_word (state, pa, data); */
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if(state->space.conf_obj != NULL)
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state->space.write(state->space.conf_obj, pa, &data, 4);
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else
|
||||
mem_write_raw(32, pa, data);
|
||||
Memory::Write32(pa, data);
|
||||
#if 0
|
||||
if (state->NumInstrs > 236403) {
|
||||
printf("write memory\n");
|
||||
@ -829,13 +796,13 @@ finished_write:
|
||||
}
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
return NO_FAULT;
|
||||
}
|
||||
|
||||
ARMword
|
||||
arm1176jzf_s_mmu_mrc (ARMul_State *state, ARMword instr, ARMword *value)
|
||||
{
|
||||
mmu_regnum_t creg = BITS (16, 19) & 0xf;
|
||||
int creg = BITS (16, 19) & 0xf;
|
||||
int OPC_1 = BITS (21, 23) & 0x7;
|
||||
int OPC_2 = BITS (5, 7) & 0x7;
|
||||
ARMword data;
|
||||
@ -921,8 +888,8 @@ arm1176jzf_s_mmu_mrc (ARMul_State *state, ARMword instr, ARMword *value)
|
||||
static ARMword
|
||||
arm1176jzf_s_mmu_mcr (ARMul_State *state, ARMword instr, ARMword value)
|
||||
{
|
||||
mmu_regnum_t creg = BITS (16, 19) & 0xf;
|
||||
mmu_regnum_t CRm = BITS (0, 3) & 0xf;
|
||||
int creg = BITS (16, 19) & 0xf;
|
||||
int CRm = BITS (0, 3) & 0xf;
|
||||
int OPC_1 = BITS (21, 23) & 0x7;
|
||||
int OPC_2 = BITS (5, 7) & 0x7;
|
||||
if (!strncmp (state->cpu->cpu_arch_name, "armv6", 5)) {
|
||||
@ -1093,56 +1060,56 @@ arm1176jzf_s_mmu_mcr (ARMul_State *state, ARMword instr, ARMword value)
|
||||
return No_exp;
|
||||
}
|
||||
|
||||
/* teawater add for arm2x86 2005.06.19------------------------------------------- */
|
||||
static int
|
||||
arm1176jzf_s_mmu_v2p_dbct (ARMul_State *state, ARMword virt_addr,
|
||||
ARMword *phys_addr)
|
||||
{
|
||||
fault_t fault;
|
||||
int ap, sop;
|
||||
|
||||
ARMword perm; /* physical addr access permissions */
|
||||
virt_addr = mmu_pid_va_map (virt_addr);
|
||||
if (MMU_Enabled) {
|
||||
|
||||
/*align check */
|
||||
if ((virt_addr & (WORD_SIZE - 1)) && MMU_Aligned) {
|
||||
d_msg ("align\n");
|
||||
return ALIGNMENT_FAULT;
|
||||
} else
|
||||
virt_addr &= ~(WORD_SIZE - 1);
|
||||
|
||||
/*translate tlb */
|
||||
fault = mmu_translate (state, virt_addr, phys_addr, &ap, &sop);
|
||||
if (fault) {
|
||||
d_msg ("translate\n");
|
||||
return fault;
|
||||
}
|
||||
|
||||
/* permission check */
|
||||
if (!check_perms(state, ap, 1)) {
|
||||
if (sop == 0) {
|
||||
return SECTION_PERMISSION_FAULT;
|
||||
} else {
|
||||
return SUBPAGE_PERMISSION_FAULT;
|
||||
}
|
||||
}
|
||||
#if 0
|
||||
/*check access */
|
||||
fault = check_access (state, virt_addr, tlb, 1);
|
||||
if (fault) {
|
||||
d_msg ("check_fault\n");
|
||||
return fault;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
if (MMU_Disabled) {
|
||||
*phys_addr = virt_addr;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
///* teawater add for arm2x86 2005.06.19------------------------------------------- */
|
||||
//static int
|
||||
//arm1176jzf_s_mmu_v2p_dbct (ARMul_State *state, ARMword virt_addr,
|
||||
// ARMword *phys_addr)
|
||||
//{
|
||||
// fault_t fault;
|
||||
// int ap, sop;
|
||||
//
|
||||
// ARMword perm; /* physical addr access permissions */
|
||||
// virt_addr = mmu_pid_va_map (virt_addr);
|
||||
// if (MMU_Enabled) {
|
||||
//
|
||||
// /*align check */
|
||||
// if ((virt_addr & (WORD_SIZE - 1)) && MMU_Aligned) {
|
||||
// DEBUG_LOG(ARM11, "align\n");
|
||||
// return ALIGNMENT_FAULT;
|
||||
// } else
|
||||
// virt_addr &= ~(WORD_SIZE - 1);
|
||||
//
|
||||
// /*translate tlb */
|
||||
// fault = mmu_translate (state, virt_addr, phys_addr, &ap, &sop);
|
||||
// if (fault) {
|
||||
// DEBUG_LOG(ARM11, "translate\n");
|
||||
// return fault;
|
||||
// }
|
||||
//
|
||||
// /* permission check */
|
||||
// if (!check_perms(state, ap, 1)) {
|
||||
// if (sop == 0) {
|
||||
// return SECTION_PERMISSION_FAULT;
|
||||
// } else {
|
||||
// return SUBPAGE_PERMISSION_FAULT;
|
||||
// }
|
||||
// }
|
||||
//#if 0
|
||||
// /*check access */
|
||||
// fault = check_access (state, virt_addr, tlb, 1);
|
||||
// if (fault) {
|
||||
// DEBUG_LOG(ARM11, "check_fault\n");
|
||||
// return fault;
|
||||
// }
|
||||
//#endif
|
||||
// }
|
||||
//
|
||||
// if (MMU_Disabled) {
|
||||
// *phys_addr = virt_addr;
|
||||
// }
|
||||
//
|
||||
// return 0;
|
||||
//}
|
||||
|
||||
/* AJ2D-------------------------------------------------------------------------- */
|
||||
|
||||
@ -71,8 +71,8 @@ u32 Read32(const u32 addr);
|
||||
u32 Read8_ZX(const u32 addr);
|
||||
u32 Read16_ZX(const u32 addr);
|
||||
|
||||
void Write8(const u32 addr, const u32 data);
|
||||
void Write16(const u32 addr, const u32 data);
|
||||
void Write8(const u32 addr, const u8 data);
|
||||
void Write16(const u32 addr, const u16 data);
|
||||
void Write32(const u32 addr, const u32 data);
|
||||
|
||||
u8* GetPointer(const u32 Address);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user